About this archived opportunity

***THIS IS A COMBINED SOURCES SOUGHT NOTICE AND NOTICE OF INTENT TO SOLE SOURCE*** The purpose of this sources sought notice is to conduct market research and identify potential sources of commercial products/services that satisfy the Government’s anticipated needs. If no alternate sources are identified, the Government intends to issue a Sole Source Award to Skywater Technology Foundry Inc, 2401 E 86th St, Bloomington, Minnesota, under the authority of FAR 13.106-1(b)(1)(i). The North American Industry Classification System (NAICS) code for this acquisition is 334413, Semiconductor and Related Device Manufacturing. BACKGROUND As part of the CHIPS R&D Program, the National Institute of Standards and Technology (NIST) requires the purchase of additional customized CMOS wafers based on a previously developed reticle set owned by NIST for a wafer-scale 0.13 um CMOS chip fabrication process. The CMOS wafers are designed to be used in developing a measurement and application testbed for novel electronic devices. Such an integrated measurement and application testbed is currently being used for parasitic-free novel device characterization as well as non-invasive imaging of complex circuits and systems. These wafers will be combined with the emerging memory technologies to allow for benchmarking the devices as stated in the initial proposal. NIST is seeking information from sources that may be capable of providing a solution that will achieve the objectives described above, in addition to the following essential requirements: Line Item 0001: Custom CMOS wafers Quantity: 12 Technical Specifications: Process flow shall be 0.13 um CMOS, Skywater FOSS SKY130 CMOS logic process node or equivalent Process shall utilize the NIST owned tooling of the NIST Nanotechnology Xccelerator reticle set The following mask/process options shall be used for the fabrication process: Single-poly and up to six metal layers Dual gate: 1.8 V core and 3.3 V I/O, including both thick and thin gate transistors Bipolar transistors Medium VT transistors Cobalt silicided source, drain and gate Shallow trench isolation Super steep retrograde twin well Deep N-well Aluminum metallization with tungsten plug FSG inter-metal dielectric Metal-Insulator-Metal (MIM) capacitor as an option, with custom placement of MIM caps between metal layers Poly resistors NIST post-processing of the finished wafers requires that the process be stopped after planarization of the fourth layer of vias and before the top metal layer is applied, leaving exposed vias on a planarized surface. Vendor MUST DELIVER WAFERS STOPPED AT THIS PROCESS STEP Vendor shall fabricate 12 ea. Engineering grade wafers using the above-mentioned reticle mask Wafers shall be bulk non-EPI silicon NIST conducted market research from May to December 2025 by performing internet searches, reviewing product literature, and speaking with vendors to determine what sources could meet NIST’s minimum requirements. The results of th